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LSM6DSO16IS Datasheet(PDF) 39 Page - STMicroelectronics |
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LSM6DSO16IS Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 107 page  9.15 CTRL10_C (19h) Control register 10 (R/W) Table 51. CTRL10_C register 0(1) 0(1) TIMESTAMP _EN 0(1) 0(1) ISPU_ CLK_SEL 0(1) 0(1) 1. This bit must be set to 0 for the correct operation of the device. Table 52. CTRL10_C register description TIMESTAMP_EN Enables timestamp counter. Default value: 0 (0: disabled; 1: enabled) The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h). ISPU_CLK_SEL Selects the ISPU core clock frequency: 0: core clock frequency set to 5 MHz (default) 1: core clock frequency set to 10 MHz 9.16 ISPU_INT_STATUS0_MAINPAGE (1Ah), ISPU_INT_STATUS1_MAINPAGE (1Bh), ISPU_INT_STATUS2_MAINPAGE (1Ch), ISPU_INT_STATUS3_MAINPAGE (1Dh) ISPU interrupt status registers (R) Table 53. ISPU_INT_STATUS0_MAINPAGE output register IA_ ISPU_7 IA_ ISPU_6 IA_ ISPU_5 IA_ ISPU_4 IA_ ISPU_3 IA_ ISPU_2 IA_ ISPU_1 IA_ ISPU_0 Table 54. ISPU_INT_STATUS1_MAINPAGE output register IA_ ISPU_15 IA_ ISPU_14 IA_ ISPU_13 IA_ ISPU_12 IA_ ISPU_11 IA_ ISPU_10 IA_ ISPU_9 IA_ ISPU_8 Table 55. ISPU_INT_STATUS2_MAINPAGE output register IA_ ISPU_23 IA_ ISPU_22 IA_ ISPU_21 IA_ ISPU_20 IA_ ISPU_19 IA_ ISPU_18 IA_ ISPU_17 IA_ ISPU_16 Table 56. ISPU_INT_STATUS3_MAINPAGE output register 0 0 IA_ ISPU_29 IA_ ISPU_28 IA_ ISPU_27 IA_ ISPU_26 IA_ ISPU_25 IA_ ISPU_24 Table 57. ISPU_INT_STATUS_MAINPAGE output register description IA_ISPU_[29:0] Generic interrupt flags from ISPU. LSM6DSO16IS CTRL10_C (19h) DS13892 - Rev 2 page 39/107 |
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