S32K311NHT0MPAST datasheet(106/143 Pages) NXP

106 / 143 page

Figure 54. RMII transmit diagram

12.8.4 Ethernet RGMII

The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/

constraints for the physical interface. Measurements are with maximum output load of 13.5pF, input transition of 1ns and pad

configured with DSE = 1'b1 and SRE = 1'b0. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Table 55. Ethernet RGMII

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

Tcyc

Clock cycle

duration 1,2

7.2

—

8.8

SRC = 0

—

TskewT

Data to clock

output skew (at

transmitter) 2

-500

—

500

SRC=0

—

TskewRi

Data to clock input

skew (at receiver) 2

—

2.6

SRC=0

—

TskewRo

Data to clock output

skew (at receiver) 2

-650

—

650

SRC=0

—

Duty_G

Clock duty cycle for

Gigabit 2

—

SRC=0

—

Duty_T

Clock duty cycle for

10/100T 2

—

SRC=0

—

Output rise time 3

—

SRC=0

—

Output fall time 3

—

SRC=0

—

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

2. RGMII timing specifications is valid for 3.3V nominal I/O pad supply voltage.

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

106 / 143

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