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S32K311NHT0MPAST Datasheet(PDF) 109 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 109 Page - NXP Semiconductors |
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109 / 143 page ![]() Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001. Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock transitions measured at mid-supply. Table 57. QuadSPI Quad 3.3V SDR 120MHz Symbol Description Min Typ Max Unit Condition Spec Number fSCK SCK clock frequency 1 — — 120 MHz Pad Loopback — fSCK SCK clock frequency 1 — — 60 MHz Internal Loopback — tSCK SCK clock period 1/fSCK — — ns Pad Loopback — tSCK SCK clock period 1/fSCK — — ns Internal Loopback — tSDC SCK duty cycle 2 45 — 55 % Internal Loopback — tSDC SCK duty cycle 2 45 — 55 % Pad Loopback — tIS Data input setup time 1.75 — — ns Pad Loopback — tIS Data input setup time 9 — — ns Internal Loopback — tIH Data input hold time 1 — — ns Pad Loopback — tIH Data input hold time 1 — — ns Internal Loopback — tOV Data output valid time — — 1.75 ns Pad Loopback — tOV Data output valid time — — 1.75 ns Internal Loopback — tIV Data output invalid time -1.5 — — ns Pad Loopback — tIV Data output invalid time -1.5 — — ns Internal Loopback — tCSSCK CS to SCK time 5 — — ns Pad Loopback — tCSSCK CS to SCK time 5 — — ns Internal Loopback — tSCKCS SCK to CS time 3 — — ns Pad Loopback — tSCKCS SCK to CS time 3 — — ns Internal Loopback — 1. This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz. 2. For S32K342 100HDQFP, tSDC spec would be 44%-56% when ENET and SAI active along with QuadSPI at 120MHZ NXP Semiconductors Communication interfaces S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 109 / 143 |
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