S32K311NHT0MPAST datasheet(112/143 Pages) NXP

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Table 59. QuadSPI Quad 3.3V SDR 103.33MHz (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tOD_DATA

Data output delay

(w.r.t. SCK)

-2.330

—

2.880

—

tOD_CS

CS output delay

(w.r.t. SCK) 2

3.391 - n/

fSCK

—

5.901 +

m/fSCK

—

tDVW

Input data valid

window 1

5.5

—

tISU_SCK

Input setup time

(w.r.t. SCK) 1

2.152

—

tIH_SCK

Input hold time (w.r.t.

SCK) 1

2.0

—

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).

2. Where m=TCSS and n=TCSH-1.

12.9.4 QuadSPI Octal 3.3V DDR 120MHz

The following table applies to S32K328, S32K338, S32K348, S32K358.

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input

transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI

trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have

pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance

of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain

upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device

Reference Manual for register and bit descriptions. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5.

Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock

transitions measured at mid-supply.

Table 60. QuadSPI Octal 3.3V DDR 120MHz

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

fSCK_DQS

SCK / DQS

frequency 1

—

120

MHz

DLL enabled

—

fSCK_DQS

SCK / DQS

frequency 1

—

120

MHz

DLL mode enabled

—

tSCK

SCK clock period

fSCK_D

—

External DQS

—

tSDC

SCK / DQS duty

cycle

—

External DQS

—

tCL_SCK_DQS

SCK / DQS low

time 1

3.75

—

Table continues on the next page...

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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