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S32K311NHT0MPAST Datasheet(PDF) 114 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 114 Page - NXP Semiconductors |
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114 / 143 page  Table 61. QuadSPI Quad 3.3V SDR 125MHz (continued) Symbol Description Min Typ Max Unit Condition Spec Number tISU_SCK Input setup time (w.r.t. SCK) 1 1.580 — — ns — — tIH_SCK Input hold time (w.r.t. SCK) 1 1.5 — — ns — — 1. Input timing assumes maximum input signal transition of 1ns (20%/80%). 2. Where m=TCSS and n=TCSH-1. 12.10 uSDHC 12.10.1 uSDHC SDR electrical specifications The following table describes the uSDHC electrical characteristics. Measurements are with maximum output load of 25pF, input transition of 1ns (20%/80%) and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux. Data transitions measured at 25%/62.5% at 3.3V for the write path. Data transitions measured at mid-supply for the read path. Clock transitions measured at mid-supply. Table 62. uSDHC SDR electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number fpp Clock frequency (low speed) 1 — — 400 kHz — SD1 fpp Clock frequency (eMMC4.4/4.41 SDR, SD3.0 SDR) 1,2 — — 50 MHz Medium/Fast Pad SD1 fpp Clock frequency (eMMC4.4/4.41 SDR, SD3.0 SDR) 1,3 — — 25 MHz Standard plus/Medium pad SD1 fOD Clock frequency (identification mode) 1 100 — 400 kHz — SD1 tWL Clock low time 6 — — ns Medium/Fast pad SD2 tWL Clock low time 12 — — ns Standard plus/Medium pad SD2 tWH Clock high time 6 — — ns Medium/Fast pad SD3 tWH Clock high time 12 — — ns Standard plus/Medium pad SD3 tTLH Clock rise time 1,4 — — 4 ns Medium/Fast pad SD4 tTLH Clock rise time 1,4 — — 8 ns Standard plus/Medium pad SD4 Table continues on the next page... NXP Semiconductors Communication interfaces S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 114 / 143 |
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