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S32K311NHT0MPAST Datasheet(PDF) 113 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 113 Page - NXP Semiconductors |
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113 / 143 page  Table 60. QuadSPI Octal 3.3V DDR 120MHz (continued) Symbol Description Min Typ Max Unit Condition Spec Number tCH_SCK_DQS SCK / DQS high time 1 3.75 — — ns — — tOD_DATA Data output delay (w.r.t. SCK) 0.816 — 2.934 ns — — tOD_CS CS output delay (w.r.t. SCK) 3.016 — -0.766 ns — — tDVW Input data valid window 1 2.518 — — ns — — tISU_DQS Input setup time (w.r.t. DQS) 1 -0.616 — — ns — — tIH_DQS Input hold time (w.r.t. DQS) 1 3.134 — — ns — — 1. Input timing assumes an input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the Flash. 12.9.5 QuadSPI Quad 3.3V SDR 125MHz The following table applies only to S32K388. The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device Reference Manual for register and bit descriptions. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux. Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock transitions measured at mid-supply. Table 61. QuadSPI Quad 3.3V SDR 125MHz Symbol Description Min Typ Max Unit Condition Spec Number fSCK SCK clock frequency 1 — — 125 MHz — — tCL_SCK SCK clock low time 1 3.6 — — ns — — tCH_SCK SCK clock high time 1 3.6 — — ns — — tOD_DATA Data output delay (w.r.t. SCK) -1.294 — 1.844 ns — — tOD_CS CS output delay (w.r.t. SCK) 2 3.391 - n/ fSCK — 3.829 + m/fSCK ns — — tDVW Input data valid window 1 4.724 — — ns — — Table continues on the next page... NXP Semiconductors Communication interfaces S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 113 / 143 |
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