S32K311NHT0MPAST datasheet(110/143 Pages) NXP

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Figure 58. QuadSPI input timing (SDR mode)

Figure 59. QuadSPI output timing (SDR mode)

12.9.2 QuadSPI Octal 3.3V DDR 100MHz

The following table applies to S32K328, S32K338, S32K348, S32K358.

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input

transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI

trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have

pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance

of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain

upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device

Reference Manual for register and bit descriptions. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.

Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5.

Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock

transitions measured at mid-supply.

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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S32K311NHT0MPAST Datasheet(PDF) 110 Page - NXP Semiconductors