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S32K311NHT0MPAST Datasheet(PDF) 108 Page - NXP Semiconductors

Part # S32K311NHT0MPAST
Description  Automotive General Purpose MCUs
PDF  143 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

S32K311NHT0MPAST Datasheet(HTML) 108 Page - NXP Semiconductors

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Table 56. MDIO timing specifications (continued)
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
invalid(minimum
propagation delay)
MDC3
MDIO (input) to
MDC rising edge
setup time
25
—
—
ns
Applies to S32K3x4,
S32K342, S32K341,
S32K322, S32K328,
S32K338, S32K348,
S32K358 and all GPIO
pads of S32K388
except GPIO[113]
MDC3
MDC3
MDIO (input) to
MDC rising edge
setup time
29.5
—
—
ns
Applies to GPIO[113]
pad of S32K388
MDC3
MDC4
MDIO (input) to
MDC rising edge
hold time
0
—
—
ns
—
MDC4
MDC (output)
MDIO (output)
MDIO (input)
MDC6
MDC5
MDC3
MDC4
MDC1
MDC2
Figure 57. MII/RMII serial management channel timing
12.9 QuadSPI
12.9.1 QuadSPI Quad 3.3V SDR 120MHz
The following table applies to S32K344, S32K324, S32K314, S32K342, S32K341, S32K322, S32K328, S32K338, S32K348,
and S32K358.
The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input
transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI
trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have
pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance
of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain
upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device
Reference Manual for register and bit descriptions. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux.
Program register value QuadSPI_FLSHCR[TCSS] = 4`h3.
Program register value QuadSPI_FLSHCR[TCSH] = 4`h3.
NXP Semiconductors
Communication interfaces
S32K3xx Data Sheet, Rev. 9.1, 03/2024
Data Sheet: Technical Data
Preliminary Information for S32K388
108 / 143



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