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AT91SAM7A2-AI Datasheet(PDF) 64 Page - ATMEL Corporation

Part # AT91SAM7A2-AI
Description  AT91 ARM Thumb-based Microcontrollers
PDF  369 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91SAM7A2-AI Datasheet(HTML) 64 Page - ATMEL Corporation

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64
PRELIMINARY
AT91SAM7A2
6021A–ATARM–07/04
When the counter reaches 0, it triggers the programmed action (internal reset or
interrupt).
If no WD reset is programmed (i.e. RSTEN is at a logical 0) when the WD reaches 0, it is
reset to the programmed value and continues to count, unless it is disabled. This
enables it to be used to generate periodic interrupts.
Block Diagram
Figure 41. Watchdog Block Diagram
Internal Reset Pulse
Generation
If the RSTEN bit is set in the WD_OMR register, an internal reset pulse is generated
when the overflow occurs. This pulse is 8 clock cycles long (CORECLK) and is not
affected by hardware reset.
After a reset (hardware or WD), the clock selected by the watchdog is LFCLK/2.
Internal Interrupt Request
The watchdog can generate an internal interrupt request when an overflow occurs. The
software can enable or disable this interrupt either in the WD module (WD_IMR register)
or in the GIC registers.
Example
The LFCLK clock source from the clock manager is used to select the WDSCLK.
The following example uses LFCLK as a value of 32.768 kHz and a pending window of
0xFF.
Example use of the Watchdog
Use of the Pending Window to generate an interrupt and reload the watchdog counter
within the window only.
PWL[15:0]
()
WDCLK
freq
--------------------------------
WD_CTR
COUNT[15:0]
WD_SR.1
WDOVF
WD_OMR.0
RSTEN
Internal
Reset
= 0
PWL[15:0]
WD_SR.0
WDPEND
RSTALW
Write Access to WD_CR
RSTKEY = 0xC071
WD_OMR.1
WDEN
WD_MR
WDPDIV[2:0]
Programmable
Divider
(WDPDIV)
D
Count
Load
16-bit
Down-counter
ENA
LFCLK
(PCV[15:0])
WDCLK
Table 32. Watch Dog Example
WD Counter
Start Value
WDPDIV[2:0]
WDCLK
Time to WD
Pending
Time to WD
Overflow
0x07FF
000
b
LFCLK/2
0.109 s
0.125 s
0x0FFF
001
b
LFCLK/4
0.468 s
0.500 s
0x17FF
010
b
LFCLK/8
1.437 s
1.500 s
0xAFFF
101
b
LFCLK/128
175 s
176 s
0xFFFF
111
b
LFCLK/1024
1040 s
2048 s



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