AT91SAM7A2-AI datasheet(16/369 Pages) ATMEL

16 / 369 page

PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

•

IP is the peak current delivered by the charge pump into the filter (typ 350 mA, min

50 mA, max 800 mA)

•

n is the division ration of the divider (i.e. PLL multiplication factor)

•

Stability can be improved with an additional capacitor C3. The value of C3 must be

chosen so that:

Equation 2:

Equation 3:

Where:

•fCKR is the PLL input frequency (i.e. MCK):

Phase jitter for the PLL is 200 ps Typically.

PLL Characteristics

Clock Timings

Core Clock

------

()

----------------------------------



 II fCKR

---------------------

≤

Table 12. PLL Characteristics

Code

Parameter

Conditions

Min

Typ

Max

Unit

CKR

Input frequency

0.02

MHz

Output frequency

MHz

Wlow

Duty cycle

Jitter

With ratio 1:1

200

Division ratio

1:1

1:1024

CO gain

105

172

MHz/V

CHP current

350

800

Table 13. Core Clock Timings

Symbol

Parameter

Minimum

Maximum

Unit

1/t

Oscillator frequency

32.768

30000

kHz

Main clock period

Main clock high time

Main clock low time

AT91SAM7A2-AI Datasheet(PDF) 16 Page - ATMEL Corporation

AT91SAM7A2-AI Datasheet(HTML) 16 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL