AT91SAM7A2-AI datasheet(52/369 Pages) ATMEL

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PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

Example

To switch from the default mode, OPE, to the LPM mode, do the following:

Configuration:

Enable the real time clock oscillator and the RTCSEL switch by writing the

RTCKEN, RTCSEL bits and CLKEKEY field in the CM_CE register.

Then wait that the RTCSEL status flag is set in the CE_CS register. Once this bit

is set, LFCLK clock is derived from the RCTK clock (see Figure 40 on page 50).

Then set the LFSLCT bit in the CM_CE register to obtain a core clock derived

from RTCK.

To change the PLL multiplier from the default mode OPE, do the following:

Disable the PLL by writing the PLLSLCT bit in CM_CD. This this enables writing

in the CM_PDIV and CM_PST registers. Now the core clock is equal to the mas-

ter oscillator clock.

Then change the PLL multiplier and the divider by 2 in the CM_PDIV register.

Users can also optimize the stabilization time of the PLL of CM_PST. This time is

used in the next step when enabling the PLL. During that time the core clock will

be cut.

Enable the PLL by writing the PLLSLCT bit in the CM_CE register. After this

action, the core clock will be stopped during the time described by the PSTB field

in the CM_PST register.

Clock Manager (CM) Memory Map

Base Address: 0xFFEC000

Table 30. Clock Manager Memory Map

Offset

Name

Access

Reset State

0x000

CM Clock Enable

CM_CE

Write-only

–

0x004

CM Clock Disable

CM_CD

Write-only

–

0x008

CM Clock Status

CM_CS

Read-only

0x00002384

0x00C

CM PLL Stabilization Time

CM_PST

Read/Write

0x000000B0

0x010

CM PLL Divider

CM_PDIV

Read/Write

0x0000800A

0x014

CM Oscillator Stabilization Time

CM_OST

Read/Write

0x000000B0

0x018

CM Master Clock Divider

CM_MDIV

Read/Write

0x0000001F

AT91SAM7A2-AI Datasheet(PDF) 52 Page - ATMEL Corporation

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