AT91SAM7A2-AI datasheet(25/369 Pages) ATMEL

25 / 369 page

PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

User Interface

Each individual MPIO is associated with a bit position in the PIO controller user interface

registers. Each of these registers is 32 bits wide. If a parallel I/O line is not defined, writ-

ing to the corresponding bit has no effect. Undefined bits read zero.

Multi-driver (Open Drain)

Each PIO can be programmed for a multi-driver option. This means that the PIO is con-

figured as open drain (can only drive a low level) in order to support external drivers on

the same pin. An external pull-up is necessary to guarantee a logic level (logical one)

when the pin is not being driven. The Peripheral_MDER (Multi-Driver Enable) and

Peripheral_MDDR (Multi-Driver Disable) registers control this option. The Multi-driver

can be selected whether the I/O pin is controlled by the PIO controller or the peripheral

controller. Peripheral_MDSR (Multi-driver Status) indicates which pins are configured to

support external drivers.

MPIO Block Diagram

Figure 8. Parallel I/O Block

Peripheral_OSR

Peripheral_PSR

Peripheral_SODR

Peripheral_MDSR

Peripheral_PSR

Peripheral_PDSR

Peripheral_SR

Peripheral_IMR

Peripheral

Output Enable

Peripheral Output

Peripheral Input

Peripheral_int

Peripheral

Controller

Pad Output Enable

Pad Output

Pad Input

Synchro

Resynch

Event

Trig

AT91SAM7A2-AI Datasheet(PDF) 25 Page - ATMEL Corporation