AT91SAM7A2-AI datasheet(31/369 Pages) ATMEL

31 / 369 page

PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

If users want to boot on a RAM memory for debug purposes, the RAM memory should

be connected the same way as a flash memory (NUB and NLB of the RAM memory

connected to the ground) to emulate a pure 16-bit Flash memory as shown in Figure 13.

Figure 15. EBI Connected to an External 16-bit RAM Memory Device, 16-bit

Access Only and Used as Boot Memory for Debug Purposes

External Bus Interface

Timings

Simple read and write access cycles are explained in detail where read access can be

done through two modes as follows:

•

The standard read protocol.

•

The early read protocol, which increases the EBI performance for read access.

The EBI can automatically insert wait states during the external access cycles. These

wait states are applied within the actual access cycle.

Data float wait states can also be inserted and applied in between cycles. The data float

wait states depend strongly on the previous and next access contingent upon whether

the state is a write or read cycle (early or standard) and if it is on the same chip select.

These conditions are detailed in the pages that follow.

Read Access

Standard Read Protocol

Standard read protocol (default read mode) implements a read cycle in which NRD/NOE

is active during the second half of the read cycle.

The first half of the read cycle allows time to ensure completion of the previous access

as well as address and NCS output before the read cycle begins.

During a standard read protocol external memory access, NCS is set low and ADDR is

valid at the beginning of the access while NRD/NOE goes low only in the second half of

the read cycle to avoid bus conflict.

Figure 16. Standard Read Address

EBI

A[21:1]

NRD

NWR0

D[15:0]

16-bit RAM

External Memory

NCS

D[15:0]

A[20:0]

NOE

NCE

NLB

NUB

NWE

Address Valid

Address

NCS

NOE/NRD

AT91SAM7A2-AI Datasheet(PDF) 31 Page - ATMEL Corporation

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