PSD4235G2-12UT datasheet(52/124 Pages) STMICROELECTRONICS

52 / 124 page

PLDS

PSD4235G2V

52/124

PLDS

The PLDs bring programmable logic functionality to the PSD. After specifying the logic for

the PLDs using PSDsoft Express, the logic is programmed into the device and available

upon Power-up.

The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The

PLDs are briefly discussed in the next few paragraphs, and in more detail in the following

sections. Figure 11 shows the configuration of the PLDs.

The DPLD performs address decoding for internal components, such as memory, registers,

and I/O ports Select signals.

The CPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, and encoding and decoding logic. These logic functions can be constructed

using the 16 output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The

CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.

The AND Array is used to form product terms. These product terms are specified using

PSDsoft Express. An input Bus consisting of 82 signals is connected to the PLDs. The

signals are shown in Table 31.

The Turbo bit in PSD

The PLDs in the PSD4235G2V can minimize power consumption by switching to standby

when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit

to ’0’ (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs

are changing. Turning the Turbo mode off increases propagation delays while reducing

power consumption. See Section 20: Power management, on how to set the Turbo bit.

Additionally, five bits are available in the PMMR2 register to block MCU control signals from

entering the PLDs. This reduces power consumption and can be used only when these

MCU control signals are not used in PLD logic equations.

Each of the two PLDs has unique characteristics suited for its applications. They are

described in the following sections.

Table 31.

DPLD and CPLD inputs

Input source

Input name

Number of

signals

MCU address bus(1)

A15-A0

MCU control signals

CNTL0-CNTL2

Reset

RST

Power-down

PDN

Port A input macrocells

PA7-PA0

Port B input macrocells

PB7-PB0

Port C input macrocells

PC7-PC0

Port D inputs

PD3-PD0

Port F inputs

PF7-PF0

PSD4235G2-12UT Datasheet(PDF) 52 Page - STMicroelectronics

PSD4235G2-12UT Datasheet(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL