 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PSD4235G2-12UT Datasheet(PDF) 95 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
PSD4235G2-12UT Datasheet(HTML) 95 Page - STMicroelectronics |
|
|
95 / 124 page  PSD4235G2V Power-on Reset, Warm Reset and Power-down 95/124 Figure 33. Reset (RESET) timing Macrocells Flip-flop status Cleared to ’0’ by internal Power-On Reset Depends on .re and .pr equations Depends on .re and .pr equations VM register(1) Initialized, based on the selection in PSDsoft Express Configuration menu Initialized, based on the selection in PSDsoft Express Configuration menu Unchanged All other registers Cleared to ’0’ Cleared to ’0’ Unchanged 1. The SR_code and Peripheral Mode bits in the VM register are always cleared to ’0’ on Power-On Reset or Warm Reset. Table 50. Status During Power-On Reset, Warm Reset and Power-down mode (continued) Port configuration Power-On Reset Warm Reset Power-down mode tNLNH-PO tOPR AI02866b RESET tNLNH tNLNH-A tOPR VCC V CC(min) Power-On Reset Warm Reset |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
