PSD4235G2-12UT datasheet(18/124 Pages) STMICROELECTRONICS

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PSD architectural overview

PSD4235G2V

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2.4

MCU bus interface

The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or non-

multiplexed address/data buses. The device is configured to respond to the MCU’s control

pins, which are also used as inputs to the PLDs.

2.5

ISP via JTAG port

In-System Programming (ISP) can be performed through the JTAG signals on Port E. This

serial interface allows complete programming of the entire PSD device. A blank device can

be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can

be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments.

2.6

In-system programming (ISP)

Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can

be programmed or erased without the use of the MCU.

2.7

In-application programming (IAP)

The primary Flash memory can also be programmed, or re-programmed, in-system by the

MCU executing the programming algorithms out of the secondary Flash memory, or SRAM.

The secondary Flash memory can be programmed the same way by executing out of the

primary Flash memory. Table 4 indicates which programming methods can program

different functional blocks of the PSD.

Table 2.

PLD I/O

Name

Inputs

Outputs

Product Terms

Decode PLD (DPLD)

Complex PLD (CPLD)

150

Table 3.

JTAG signals on port E

Port E pins

JTAG signal

PE0

TMS

PE1

TCK

PE2

TDI

PE3

TDO

PE4

TSTAT

PE5

TERR

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