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PSD4235G2-12UT Datasheet(PDF) 22 Page - STMicroelectronics

Part # PSD4235G2-12UT
Description  Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
PDF  124 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2-12UT Datasheet(HTML) 22 Page - STMicroelectronics

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PSD register description and address offsets
PSD4235G2V
22/124
4
PSD register description and address offsets
Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space.
The following sections give a more detailed description.
Table 5.
Register address offset
Register name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Other(1)
Description
Data In
00
01
10
11
30
40
41
Reads Port pin as input, MCU I/O
input mode
Control
32
42
43
Selects mode between MCU I/O or
Address Out
Data Out
04
05
14
15
34
44
45
Stores data for output to Port pins,
MCU I/O output mode
Direction
06
07
16
17
36
46
47
Configures Port pin as input or output
Drive Select
08
09
18
19
38
48
49
Configures Port pins as either CMOS
or Open Drain on some pins, while
selecting high slew rate on other pins.
Input macrocell
0A
0B
1A
Reads input macrocells
Enable Out
0C
0D
1C
4C
Reads the status of the output enable
to the I/O Port driver
Output
macrocells A
20
READ - reads output of macrocells A
WRITE - loads macrocell Flip-flops
Output
macrocells B
21
READ - reads output of macrocells B
WRITE - loads macrocell Flip-flops
Mask
macrocells A
22
Blocks writing to the output macrocells
A
Mask
macrocells B
23
Blocks writing to the output macrocells
B
Flash Memory
Protection
C0
Read only - Primary Flash Sector
Protection
Flash Boot
Protection
C2
Read only - PSD Security and
secondary Flash memory Sector
Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
Page
E0
Page register
VM
E2
Places PSD memory areas in
Program and/or Data space on an
individual basis.



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