PSD4235G2-12UT datasheet(28/124 Pages) STMICROELECTRONICS

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PSD4235G2V

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APD Enable:

0: Automatic Power-down (APD) is disabled.

1: Automatic Power-down (APD) is enabled.

PLD Turbo:

0: PLD Turbo is on.

1: PLD Turbo is off, saving power.

PLD Array CLK:

0: CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD

when Turbo bit is off.

1: CLKIN to the PLD AND array is disconnected, saving power.

PLD MCells CLK:

0: CLKIN to the PLD macrocells is connected.

1: CLKIN to the PLD macrocells is disconnected, saving power.

5.16

PMMR2 register

For bit 4, bit 3, bit 2: See Table 33 for the signals that are blocked on pins CNTL0-CNTL2.

PLD Array Addr:

0: Address A7-A0 are connected to the PLD array.

1 Address A7-A0 are blocked from the PLD array, saving power.

Note:

In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4).

PLD Array CNTL2:

0: CNTL2 input to the PLD AND array is connected.

1: CNTL2 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL1

0: CNTL1 input to the PLD AND array is connected.

1: CNTL1 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL0

0: CNTL0 input to the PLD AND array is connected.

1: CNTL0 input to the PLD AND array is disconnected, saving power.

PLD Array ALE

0: ALE input to the PLD AND array is connected.

1: ALE input to the PLD AND array is disconnected, saving power.

Table 23.

PMMR2 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to ’0’)

PLD

Array

WRH

PLD

Array ALE

PLD Array

CNTL2

PLD Array

CNTL1

PLD Array

CNTL0

not used

(set to ’0’)

PLD

Array Addr

PSD4235G2-12UT Datasheet(PDF) 28 Page - STMicroelectronics

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