PSD4235G2-12UT datasheet(72/124 Pages) STMICROELECTRONICS

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MCU bus interface

PSD4235G2V

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18.9

MMC2001

The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external

boot ROM. The PSD can be configured as the external flash boot ROM or as extension to

the internal ROM.

The MMC2001 has a 16-bit external data bus and 20 address lines with external chip select

signals. The Chip Select Control registers allow the user to customize the bus interface and

timing to fit the individual system requirement. A typical interface configuration to the PSD is

shown in Figure 24. The MMC2001’s R/W signal is connected to the CNTL0 pin, while EB0

and EB1 (enable byte-0 and enable byte-1) are connected to the CNTL1 (UDS) and CNTL2

(LDS) pins. The WEN bit in the Chip Select Control register should be set to ’1’ to terminate

the EB0-EB1 earlier to provide the write data hold time for the PSD. The WSC and WWS

bits in the Control register are set to wait states that meet the PSD access time requirement.

Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case, the

PSD control setting will be: OE, WRL, WRH where OE is the READ signal for the

MMC2001.

18.10

C16x family

The PSD supports Infineon’s C16X family of MCUs (C161-C167) in both the multiplexed and

non-multiplexed bus configuration. In Figure 25, the C167CR is shown connected to the

PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE

and ALE, and are routed to the corresponding PSD pins.

The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported

by the PSD.

PSD4235G2-12UT Datasheet(PDF) 72 Page - STMicroelectronics