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PSD4235G2-12UT Datasheet(PDF) 93 Page - STMicroelectronics |
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PSD4235G2-12UT Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 124 page  PSD4235G2V Power management 93/124 20.7 Input control signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable high-byte (WRH/DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a ’1’ in PMMR2. Table 49. APD counter operation APD Enable bit ALE PD polarity ALE level APD counter 0 X X Not counting 1 X Pulsing Not counting 1 1 1 Counting (Generates PDN after 15 clocks) 1 0 0 Counting (Generates PDN after 15 clocks) |
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