PSD4235G2-12UT datasheet(35/124 Pages) STMICROELECTRONICS

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PSD4235G2V

Instructions

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Instructions

An instruction consists of a sequence of specific operations. Each received byte is

sequentially decoded by the PSD and not executed as a standard WRITE operation. The

instruction is executed when the correct number of bytes are properly received and the time

between two consecutive bytes is shorter than the timeout period. Some instructions are

structured to include READ operations after the initial WRITE operations.

The instruction must be followed exactly. Any invalid combination of instruction bytes or

timeout between two consecutive bytes while addressing Flash memory resets the device

logic into READ mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in Table 28:

●

Erase memory by chip or sector

●

Suspend or resume sector erase

●

Program a Word

●

Reset to READ mode

●

Read primary Flash Identifier value

●

Read Sector Protection Status

●

Bypass

These instructions are detailed in Table 28. For efficient decoding of the instructions, the first

two bytes of an instruction are the coded cycles and are followed by an instruction byte or

confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh

during the first cycle and data 55h to address X554h during the second cycle (unless the

Bypass instruction feature is used, as described later). Address signals A15-A12 are Don’t

Care during the instruction WRITE cycles. However, the appropriate Sector Select signal

(FS0-FS7, or CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have the same instruction set (except for Read

Primary Flash Identifier). The Sector Select signals determine which Flash memory is to

receive and execute the instruction. The primary Flash memory is selected if any one of its

Sector Select signals (FS0-FS7) is high, and the secondary Flash memory is selected if any

one of its Sector Select signals (CSBOOT0-CSBOOT3) is high.

7.1

Power-up condition

The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7

and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR/WRL, CNTL0) high,

during Power-up for maximum security of the data contents and to remove the possibility of

data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any WRITE cycle

initiation is locked when VCC is below VLKO.

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