PSD4235G2-12UT datasheet(29/124 Pages) STMICROELECTRONICS

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PSD4235G2V

29/124

PLD Array WRH

0: WRH/DBE input to the PLD AND array is connected.

1: WRH/DBE input to the PLD AND array is disconnected, saving power.

5.17

VM register

On reset, bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft

Express. bit0 and bit7 are always cleared on reset. bit0-Bit4 are active only when the device

is configured in Philips 80C51XA mode.

SR_code

0 = PSEN cannot access SRAM in 80C51XA modes.

1 = PSEN can access SRAM in 80C51XA modes.

Boot_code

0 = PSEN cannot access secondary NVM in 80C51XA modes.

1 = PSEN can access secondary NVM in 80C51XA modes.

FL_code

0 = PSEN cannot access primary Flash memory in 80C51XA modes.

1 = PSEN can access primary Flash memory in 80C51XA modes.

Boot_data

0 = RD cannot access secondary NVM in 80C51XA modes.

1 = RD can access secondary NVM in 80C51XA modes.

FL_data

0 = RD cannot access primary Flash memory in 80C51XA modes.

1 = RD can access primary Flash memory in 80C51XA modes.

Peripheral mode

0 = Peripheral mode of Port F is disabled.

1 = Peripheral mode of Port F is enabled.

Table 24.

VM register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Peripheral

mode

not used

(set to ’0’)

not used

(set to ’0’)

FL_data

Boot_data

FL_code

Boot_code SR_code

PSD4235G2-12UT Datasheet(PDF) 29 Page - STMicroelectronics

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