PSD4235G2-12UT datasheet(48/124 Pages) STMICROELECTRONICS

Part #	PSD4235G2-12UT

Description	Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)

PDF	124 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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Memory Select signals

PSD4235G2V

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when desired.

Table 24 describes the VM register.

Figure 7.

Priority level of memory and I/O components

12.3

Separate space modes

Program space is separated from Data space. For example, Program Select Enable (PSEN,

CNTL2) is used to access the program code from the primary Flash memory, while Read

Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and

I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 8).

12.4

Combined space modes

The Program and Data spaces are combined into one memory space that allows the

primary Flash memory, secondary Flash memory, and SRAM to be accessed by either

Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to

configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are

set to ’1’ (see Figure 9).

Level 1

SRAM, I /O, or

Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

AI02867D

PSD4235G2-12UT Datasheet(PDF) 48 Page - STMicroelectronics