PSD4235G2-12UT datasheet(27/124 Pages) STMICROELECTRONICS

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PSD4235G2V

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5.12

Flash Boot Protection register

Sec<i>_Prot:

1: Secondary Flash memory Sector <i> is write protected.

0: Secondary Flash memory Sector <i> is not write protected.

Security_Bit:

0: Security bit in device has not been set.

1: Security bit in device has been set.

5.13

JTAG Enable register

JTAGEnable:

1: JTAG Port is enabled.

0: JTAG Port is disabled.

5.14

Page register

This register configures the page input to PLD.

Default value is PGR7-PGR0=0.

5.15

PMMR0 register

The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET)

pulses do not clear the registers.

Table 19.

Flash Boot Protection register

Bit 7Bit 6

Bit 5Bit 4Bit 3

Bit 2Bit 1Bit 0

Security_

Bit

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Table 20.

JTAG Enable register

Bit 7Bit 6

Bit 5Bit 4Bit 3

Bit 2Bit 1Bit 0

not used

JTAG

Enable

Table 21.

Page register

Bit 7Bit 6

Bit 5Bit 4Bit 3

Bit 2Bit 1Bit 0

PGR 7

PGR 6

PGR 5

PGR 4

PGR 3

PGR 2

PGR 1

PGR 0

Table 22.

PMMR0 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to ’0’)

not used

(set to ’0’)

PLD

MCells

CLK

PLD

Array CLK

PLD

Turbo

not used

(set to ’0’)

APD

Enable

not used

(set to ’0’)

PSD4235G2-12UT Datasheet(PDF) 27 Page - STMicroelectronics

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