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PSD4235G2-12UT Datasheet(PDF) 87 Page - STMicroelectronics |
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PSD4235G2-12UT Datasheet(HTML) 87 Page - STMicroelectronics |
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87 / 124 page ![]() PSD4235G2V I/O ports 87/124 19.24 Port F - functionality and structure Port F can be configured to perform one or more of the following functions: ● MCU I/O Mode ● CPLD output - External Chip Select (ECS7-ECS0) can be connected to Port F or Port C. ● CPLD input - direct input to the CPLD, no input macrocells (IMC) ● Latched Address output - Provide latched address output as per Table 40. ● Slew Rate - pins can be configured for fast Slew Rate ● Data Port - connected to D7-D0 when Port F is configured as Data Port for a non- multiplexed bus ● Peripheral Mode ● MCU Reset Mode - for 16-bit Motorola 683xx and HC16 MCUs 19.25 Port G - functionality and structure Port G can be configured to perform one or more of the following functions: ● MCU I/O Mode ● Latched Address output - Provide latched address output as per Table 40. ● Open Drain - pins can be configured in Open Drain Mode ● Data Port - connected to D15-D8 when Port G is configured as Data Port for a non- multiplexed bus ● MCU Reset Mode - for 16-bit Motorola 683xx and hc16 mcus |
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