PSD4235G2-12UT datasheet(47/124 Pages) STMICROELECTRONICS

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PSD4235G2V

Memory Select signals

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Memory Select signals

The Primary Flash Memory Sector Select (FS0-FS7), Secondary Flash Memory Sector

Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD.

They are defined using PSDsoft Express. The following rules apply to the equations for

these signals:

●

Primary Flash memory and secondary Flash memory Sector Select signals must not

be larger than the physical sector size.

●

Any primary Flash memory sector must not be mapped in the same memory space as

another Flash memory sector.

●

A secondary Flash memory sector must not be mapped in the same memory space as

another secondary Flash memory sector.

●

SRAM, I/O, and Peripheral I/O spaces must not overlap.

●

A secondary Flash memory sector may overlap a primary Flash memory sector. In

case of overlap, priority is given to the secondary Flash memory sector.

●

SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is

given to the SRAM, I/O, or Peripheral I/O.

12.1

Example

FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from

8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0

always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh

(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any

address greater than 9FFFh accesses the primary Flash memory segment 0. You can see

that half of the primary Flash memory segment 0 and one-fourth of secondary Flash

memory segment 0 cannot be accessed in this example. Also note that an equation that

defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.

Figure 7 shows the priority levels for all memory components. Any component on a higher

level can overlap and has priority over any component on a lower level. Components on the

same level must not overlap. level 1 has the highest priority and level 3 has the lowest.

12.2

Memory Select configuration for MCUs with separate

Program and Data spaces

The 80C51XA and compatible family of MCUs, can be configured to have separate address

spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and

Data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the

PSD can reside in either space or both spaces. This is controlled through manipulation of

the VM register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to have an initial value. It can subsequently

be changed by the MCU so that memory mapping can be changed on-the-fly.

For example, you may wish to have SRAM and primary Flash memory in the Data space at

Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the

secondary Flash memory and primary Flash memory. This is easily done with the VM

PSD4235G2-12UT Datasheet(PDF) 47 Page - STMicroelectronics

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