MPF7100BVBA2ES datasheet(19/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

19 / 125

When OTP_SW_MODE = 1, the default values of the SWx_STBY_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_STBY_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to

1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the

LDOx_RUN_EN bit is set to 0 (disabled) by default.

Upon power up, the standby registers are loaded with the same default OTP values as

the run mode. The MCU is expected to program the desired standby values during boot

up.

If any of the external regulators are disabled in the standby state, the power down

sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the

WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register.

If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic

watchdog failure, it powers down the external regulators and proceeds to the fail-safe

transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD

reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event

initiated by the internal watchdog counter as described in Section 15.10.2 "Watchdog

reset behaviors".

13.1.8 Power down state

During power down state, all regulators except VSNVSx are disabled as configured in

the power down sequence. The power down sequence is programmable as defined in

Section 14.6.2 "Power down sequencing".

Two types of events may lead to the power down sequence:

• Non-faulty turn off events: move directly into LP_Off state as soon as power down

sequence is finalized

• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized

13.1.9 Fail-safe transition

The fail-safe transition is entered if the PF7100 initiates a turn off event due to a PMIC

fault.

If the fail-safe transition is entered, the PF7100 provides four FAIL bits to indicate the

source of the failure:

• The PU_FAIL is set to 1 when the device shuts down due to a power up failure

• The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter

max out

• The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault

counter maxed out or fault timer expired)

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