MPF7100BVBA2ES datasheet(20/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

20 / 125

• The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown

The value of the FAIL bits is retained as long as VIN > UVDET.

The MCU can read the FAIL bits during the system-on states in order to obtain

information about the previous failure and can clear them by writing a 1 to them, provided

the state machine is able to power up successfully after such failure.

In the PF7100 ASIL B part numbers, when the state machine enters the fail-safe

transition, a fail-safe counter is compared and increased, if the FS_CNT[3:0] reaches the

maximum count, the device can be programmed to move directly to the fail-safe state to

prevent a cyclic failure from happening.

13.1.10 Fail-safe state (ASIL B only)

The fail-safe state works as a safety lock-down upon a critical device/system failure. It is

reached when the FS_CNT [3:0] = FS_MAX_CNT [3:0].

A bit is provided to enable or disable the device to enter the fail-safe state upon a cyclic

failure. When the OTP_FS_BYPASS = 1, the fail-safe bypass operation is enabled and

the device always move to the LP_Off state, regardless of the value of the FS_CNT[3:0].

If the OTP_FS_BYPASS = 0, the fail-safe bypass is disabled, and the device moves to

the fail-safe state when the proper condition is met.

The maximum number of times the device can pass through the fail-safe

transition continuously prior to moving to a fail state is programmed by the

OTP_FS_MAX_CNT[3:0] bits. If the FS_MAX_CNT[3:0] = 0x00, the device moves into

the fail-safe state as soon as it fails for the very first time.

If the FSOB pin is programmed to assert upon a specific fault, the FSOB pin remains

asserted low during the fail-safe state if the corresponding fault is present when the

PF7100 reaches the fail-safe state.

The device can exit the fail-safe state only after a power cycle (VIN crossing UVDET)

event is present.

To avoid reaching the fail-safe state due to isolated fail-safe transition events,

the FS_CNT [3:0] is gradually decreased based on a fail-safe OK timer. The

OTP_FS_OK_TIME[2:0] bits select the default time configuration for the fail-safe OK

timer between 1 to 60 min.

Table 12. Fail-safe OK timer configuration

OTP_FS_OK_TIME[2:0]

FS_CNT decrease period (min)

000

001

010

011

100

101

110

111

When the fail-safe OK timer reaches the configured time during the system-on states, the

state machine decreases the FS_CNT[3:0] bits by one and starts a new count until the

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