MPF7100BVBA2ES datasheet(36/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

36 / 125

Table 26. Fault bypass bits

Regulator

Bit to bypass a current

limit

Bit to bypass an

undervoltage

Bit to bypass an

overvoltage

SW1

SW1_ILIM_BYPASS

SW1_UV_BYPASS

SW1_OV_BYPASS

SW2

SW2_ILIM_BYPASS

SW2_UV_BYPASS

SW2_OV_BYPASS

SW3

SW3_ILIM_BYPASS

SW3_UV_BYPASS

SW3_OV_BYPASS

SW4

SW4_ILIM_BYPASS

SW4_UV_BYPASS

SW4_OV_BYPASS

SW5

SW5_ILIM_BYPASS

SW5_UV_BYPASS

SW5_OV_BYPASS

LDO1

LDO1_ILIM_BYPASS

LDO1_UV_BYPASS

LDO1_OV_BYPASS

LDO2

LDO2_ILIM_BYPASS

LDO2_UV_BYPASS

LDO2_OV_BYPASS

The default value of the OV_BYPASS, UV_BYPASS and ILIM_BYPASS bits upon power

up can be configured by their corresponding OTP bits.

Bypassing the fault detection prevents the specific fault from starting any of the protective

mechanisms:

• Increment the counter

• Start the fault timer

• Disable the regulator if the corresponding _STATE bit is 0

• OV / UV condition asserting the PGOOD pin low

When a fault is bypassed, the corresponding interrupt bit is still set and the INTB pin is

asserted, provided the interrupt has not been masked.

14.7.1 Fault monitoring during power up state

An OTP bit is provided to select whether the output of the switching regulators is

verified during the power up sequence and used as a gating condition to release the

RESETBMCU or not.

• When OTP_PG_CHECK = 0, the output voltage of the regulators is not checked during

the power up sequence and power good indication is not required to de-assert the

RESETBMCU. In this scenario, the OV/UV monitors are masked until RESETBMCU

is released; after this event, all regulators may start checking for faults after their

corresponding blanking period.

• When OTP_PG_CHECK = 1, the output voltage of the regulators is verified during

the power up sequence and a power good condition is required to release the

RESETBMCU.

When OTP_PG_CHECK = 1, OV and UV faults during the power up sequence are

reported based on the internal PG (Power Good) signals of the corresponding external

regulator. The PGOOD pin can be used as an external indicator of an OV/UV failure

when the RESETBMCU is ready to be de-asserted and it has been configured in the

PGOOD mode. See Section 14.9.8 "PGOOD" for details on PGOOD pin operation and

configuration.

Regardless of the PGOOD pin configured as a power good indicator or not, the PF7100

masks the detection of an OV/UV failure until RESETBMCU is ready to be released, at

this point the device checks for any OV/UV condition for the regulators turned on so far.

If all regulators powered up before or in the same sequence slot than RESETBMCU are

in regulation, RESETBMCU is de-asserted and the power up sequence can continue as

shown in Figure 15.

MPF7100BVBA2ES Datasheet(PDF) 36 Page - NXP Semiconductors

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