MPF7100BVBA2ES datasheet(87/125 Pages) NXP

87 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

87 / 125

Table 70. Thermal monitor bit description

Bit(s)

Description

THERM_80_I, THERM_80_S, THERM_80_M

Interrupt, sense, and mask bits for 80 ºC threshold

THERM_95_I, THERM_95_S, THERM_95_M

Interrupt, sense, and mask bits for 95 ºC threshold

THERM_110_I, THERM_110_S, THERM_110_M

Interrupt, sense, and mask bits for 110 ºC threshold

THERM_125_I, THERM_125_S, THERM_125_M

Interrupt, sense, and mask bits for 125 ºC threshold

THERM_140_I, THERM_140_S, THERM_140_M

Interrupt, sense, and mask bits for 140 ºC threshold

THERM_155_I, THERM_155_S, THERM_155_M

Interrupt, sense, and mask bits for 155 ºC threshold

TMP_MON_EN

Disables temperature monitoring circuits when

cleared

TMP_MON_AON

When set, the temperature monitoring circuit is always

ON.

When cleared, the temperature monitor operates in

sampling mode.

15.9 Analog multiplexer

An analog multiplexer (AMUX) is provided to allow access to various internal voltages

within the PMIC. The selected voltage is buffered and made available on the AMUX

output pin during the system-on states.

When the AMUX_EN bit is 0, the AMUX block is disabled and the output remains pulled

down to ground.

When the AMUX_EN bit is 1, the AMUX block is enabled and the system may select the

channel to be read by using the AMUX_SEL[4:0] bits.

Table 71. AMUX channel selection

AMUX_EN

AMUX_SEL[4:0]

AMUX selection

Internal signal dividing ratio

X XXXX

AMUX disabled and pin pulled down to

ground

N/A

0 0000

AMUX disabled in high impedance mode N/A

0 0001

VIN

0 0010

VSNVS1

3.5

0 0011

VSNVS2

0 0100

SW1_FB

1.25 (1.8 V setting)

1 (all other settings)

0 0101

SW2_FB

1.25 (1.8 V setting)

1 (All other settings)

0 0110

SW3_FB

1.25 (1.8 V setting)

1 (all other settings)

0 0111

SW4_FB

1.25 (1.8 V setting)

1 (all other settings)

0 1000

SW5_FB

10/3.5 = 2.86

0 1011

LDO1

10/5 = 2 (0.8 V to 1.2 V settings)

10/3 = 3.33 (1.5 V to 5.0 V settings)

0 1100

LDO2

10/5 = 2 (0.8 V to 1.2 V settings)

10/3 = 3.33 (1.5 V to 5.0 V settings)

0 1111

TEMP_IC

MPF7100BVBA2ES Datasheet(PDF) 87 Page - NXP Semiconductors

MPF7100BVBA2ES Datasheet(HTML) 87 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL