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MPF7100BVBA2ES Datasheet(PDF) 7 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 7 / 125 9 ESD ratings Table 5. ESD ratings All ESD specifications are compliant with AEC-Q100 specification. Symbol Parameter Min Typ Max Unit VESD Human Body Model [1] — — 2000 V VESD Charge Device Model QFN package - all pins [1] — — 500 V ILATCHUP Latch-up current — — 100 mA [1] ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), robotic (CZAP = 4.0 pF) 10 Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Min Typ Max Unit TA Ambient operating temperature AEC-Q100 grade 1 −40 — 125 °C TA Ambient operating temperature AEC-Q100 grade 2 −40 — 105 °C TJ Junction temperature −40 — 150 °C TST Storage temperature range −55 — 150 °C TPPRT Peak package reflow temperature — — 260 °C Table 7. HVQFN48 thermal resistance and package dissipation ratings Symbol Parameter Min Max Unit RθJA Junction to ambient thermal resistance Four layer board (2s2p) [1] [2] [3] — 35 °C/W RθJA Junction to ambient thermal resistance Eight layer board (2s6p) [1] [2] [4] — 22 °C/W ΨJT Junction-to-top of package thermal resistance Four layer board(2s2p) [1] [2] [3] — 1.0 °C/W ΨJT Junction-to-top of package thermal resistance Eight layer board(2s6p) [1] [2] [4] — 1.0 °C/W [1] Determined in accordance to JEDEC JESD51-2A natural convection environment and uniform power. [2] Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment.It is not meant to predict the performance of a package in an application-specific environment. [3] Thermal test board meets JEDEC specification for this package (JESD51-9, 2s2p). [4] 2s6p PCB is with customized board layers (top and bottom metal layers are at 7 μm thickness, internal metal layers are at 35 µm thickness). 11 Operating conditions Table 8. Operating conditions Symbol Parameter Min Typ Max Unit VIN Main input supply voltage UVDET — 5.5 V |
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