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MPF7100BVBA2ES Datasheet(PDF) 94 Page - NXP Semiconductors

Part # MPF7100BVBA2ES
Description  7-channel power management integrated circuit for high performance applications
PDF  125 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF7100BVBA2ES Datasheet(HTML) 94 Page - NXP Semiconductors

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NXP Semiconductors
PF7100
7-channel power management integrated circuit for high performance applications
PF7100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 9 March 2021
94 / 125
Each time a WD event occurs, the WD_EVENT_CNT[3:0] nibble is incremented.
To prevent continuous failures, if the WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0]
the state machine proceeds to the fail-safe transition. The MCU is expected to
clear the WD_EVENT_CNT[3:0] when it is able to do so in order to keep proper
operation. Upon power up, the WD_MAX_CNT[3:0] is loaded with the values on the
OTP_WD_MAX_CNT[3:0] bits.
Every time the device passes through the Off states, the WD_EVENT_CNT[3:0] is reset
to 0x00, to ensure that the counter has a fresh start after a device power down.
WD_EVENT_CNT
reset by Fail-safe
Transition
WD_EVENT_CNT
reset by MCU
aaa-028075
WD_EVENT_CNT
WD EVENT
WD EVENT
WD EVENT
WD EVENT
WD EVENT
WD EVENT
FAIL-SAFE
TRANSITION
n =
WD_MAX
_CNT
5
4
3
2
1
0
Figure 39. Watchdog event counter
16 I2C register map
The PF7100 provides a complete set of registers for control and diagnostics of the PMIC
operation. The configuration of the device is done at two different levels.
At first level, the OTP Mirror registers provide the default hardware and software
configuration for the PMIC upon power up. These are one-time programmable and
should be defined during the system development phase, and are not meant to be
modified during the application. See Section 17 "OTP/TBB and hardwire default
configurations" for more details on the OTP configuration feature.
At a second level, the PF7100 provides a set of functional registers intended for
system configuration and diagnostics during the system operation. These registers are
accessible during the system-on states and can be modified at any time by the System
Control Unit.



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