MPF7100BVBA2ES datasheet(40/125 Pages) NXP

40 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

40 / 125

• When the mask bit is 0, INTB pin is pulled low as long as the corresponding latch bit is

set.

• The sense bit XXXX_S: if available, the sense bit provides the actual status of the

signal triggering the interrupt.

The INTB pin is a reflection of an “OR” logic of all the interrupt status bits which control

the pin.

Interrupts are stored in two levels on the interrupts registers. At first level, the SYS_INT

event.

The corresponding SYS_INT bits are set as long as the INTB pin is programmed to

assert with any of the interrupt bits of the respective interrupt registers.

• STATUS1_I: this bit is set when the interrupt is generated within the INT STATUS1

• STATUS2_I: this bit is set when the interrupt is generated within the INT STATUS2

• MODE_I: this bit is set when the interrupt is generated within the SW MODE INT

• ILIM_I: this bit is set when the interrupt is generated within any of the SW ILIM INT or

LDO ILIM INT registers

• UV_I: this bit is set when the interrupt is generated within any of the SW UV INT or

LDO UV INT registers

• OV_I: this bit is set when the interrupt is generated within any of the SW OV INT or

LDO OV INT registers

• PWRON_I: this bit is set when the interrupt is generated within the PWRON INT

• EWARN_I: is set when an early warning event occurs to indicate an imminent

shutdown.

The SYS_INT bits are set when the INTB pin is asserted by any of the second level

interrupt bits that have not been masked in their corresponding mask registers. When

the second level interrupt bit is cleared, the corresponding first level interrupt bit on the

SYS_INT register is cleared automatically.

The INTB pin remains asserted if any of the first level interrupts bit is set, and is de-

asserted only when all the unmasked second level interrupts are cleared and thus all the

first level interrupts are cleared as well.

At second level, the remaining registers provide the exact source for the interrupt event.

Table 27 shows a summary of the interrupt latch, mask, and sense pins available on the

PF7100.

Table 27. Interrupt registers

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

INT STATUS1

SDWN_I

FREQ_RDY_I

CRC_I

PWRUP_I

PWRDN_I

XINTB_I

FSOB_I

VIN_OVLO_I

INT MASK1

SDWN_M

FREQ_RDY_M

CRC_M

PWRUP_M

PWRDN_M

XINTB_M

FSOB_M

VIN_OVLO_M

INT SENSE1

—

XINTB_S

FSOB_S

VIN_OVLO_S

THERM INT

WDI_I

FSYNC_FLT_I

THERM_155_I

THERM_140_I

THERM_125_I

THERM_110_I

THERM_95_I

THERM_80_I

THERM MASK

WDI_M

FSYNC_FLT_M

THERM_155_M

THERM_140_M

THERM_125_M

THERM_110_M

THERM_95_M

THERM_80_M

THERM SENSE

WDI_S

FSYNC_FLT_S

THERM_155_S

THERM_140_S

THERM_125_S

THERM_110_S

THERM_95_S

THERM_80_S

SW MODE INT

—

SW5_MODE_I

—

SW4_MODE_I

SW3_MODE_I

SW2_MODE_I

SW1_MODE_I

SW MODE MASK

—

SW5_MODE_M

—

SW4_MODE_M

SW3_MODE_M

SW2_MODE_M

SW1_MODE_M

SW ILIM INT

—

SW5_ILIM_I

—

SW4_ILIM_I

SW3_ILIM_I

SW2_ILIM_I

SW1_ILIM_I

SW ILIM MASK

—

SW5_ILIM_M

—

SW4_ILIM_M

SW3_ILIM_M

SW2_ILIM_M

SW1_ILIM_M

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