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MPF7100BVBA2ES Datasheet(PDF) 76 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 76 Page - NXP Semiconductors |
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76 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 76 / 125 • LDO1 and LDO2 A programmable UV threshold is selected via the OTP_SWxUV_TH[1:0] and OTP_LDOxUV_TH[1:0] bits. UV threshold selection represents a percentage of the nominal voltage programmed on each regulator. Table 62. UV threshold configuration register OTP_SWxUV_TH[1:0] OTP_LDOxUV_TH[1:0] UV threshold level 00 95 % 01 93 % 10 91 % 11 89 % A programmable OV threshold is selected via the OTP_SWxOV_TH[1:0] and OTP_LDOxOV_TH[1:0] bits. OV threshold selection represents a percentage of the nominal voltage programmed on each regulator. Table 63. OV threshold configuration register OTP_SWxOV_TH OTP_LDOxOV_TH OV threshold level 00 105 % 01 107 % 10 109 % 11 111 % Two functional bits are provided to program the UV debounce time for all the voltage regulators. Table 64. UV debounce timer configuration UV_DB[1:0] UV debounce time 00 5 µs 01 15 µs 10 25 µs 11 40 µs The default value of the UV_DB[1:0] upon a full register reset is 0b10. Two functional bits to program the OV debounce time for all the voltage regulators. Table 65. OV debounce timer configuration OV_DB[1:0] OV debounce time 00 30 µs 01 50 µs 10 80 µs 11 125 µs The default value of the OV_DB[1:0] upon a full register reset is 0b00. The VMON_EN bits enable or disable the OV/UV monitor for each one of the external regulators (SWxVMON_EN, LDOxVMON_EN). |
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