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MPF7100BVBA2ES Datasheet(PDF) 73 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 73 / 125 aaa-028066 I2C INTERFACE discharge VLDOx VLDOxIN VBG1 2.5 to 5.5 V CINLDOx COLDOx LDOxEN VLDOx[3:0] Figure 30. LDOx regulator block diagram LDO1 and LDO2 have their own dedicated input supply pin, LDO1IN and LDO2IN respectively. The two LDOs are provided with 1 bit to enable or disable its output during the system-on states. • When LDOx_RUN_EN = 0, the LDO is disabled during the run mode. If the regulator is part of the power up sequence, this bit is set during the power up sequence. Otherwise it is defaulted to 0. • When LDOx_STBY_EN = 0, the LDO is disabled during the standby mode. If the regulator is part of the power up sequence, this bit is set during the power up sequence. Otherwise it is defaulted to 0. The mode of operation of the LDOx is selected on OTP via the OTP_LDOxLS bit. Table 59. LDO operation description LDOx_RUN_EN / LDOx_STBY_ EN OTP_LDOxLS LDO operation mode (Run or standby mode) 0 X Disabled with output pulldown active 1 0 Enabled in normal mode 1 1 Enabled in load switch configuration The LDOs use 4 bits to set the output voltage. • The VLDOx_RUN[3:0] sets the output voltage during the run mode. • The VLDOx_STBY[3:0] sets the output voltage during standby mode. The default output voltage configuration for the run and the standby modes is loaded from the OTP_VLDOx[3:0] registers on power up. |
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