MPF7100BVBA2ES datasheet(54/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

54 / 125

14.9.14.2 I2C secure write

A secure write mechanism is implemented for specific registers critical to the functional

safety of the device.

• When OTP_I2C_ SECURE_EN = 0, the secure write is disabled.

• When OTP_I2C_ SECURE_EN = 1, the secure write is enabled.

When the secure write is enabled, a specific sequence must be followed in order to grant

writing access on the corresponding secure register.

Secure write sequence is as follows:

• MCU sends command to modify the secure registers

• PMIC generates a random code in the RANDOM_GEN register

• MCU reads the random code from the RANDOM_GEN register and writes it back on

the RANDOM_CHK register

The PMIC compares the RANDOM_CHK against the RANDOM_GEN register:

• If RANDOM_CHK [7:0] = RANDOM_GEN[7:0], the device applies the configuration

on the corresponding secure register, and self-clears both the RANDOM_GEN and

RANDOM_CHK registers.

• If RANDOM_CHK[7:0] different from RANDOM_GEN[7:0], the device ignores the

configuration command and self-clears both the RANDOM_GEN and RANDOM_CHK

registers.

In the event the MCU sends any other command instead of providing a value for the

RANDOM_CHK register, the state machine cancels the ongoing secure write transaction

and performs the new I2C command.

In the event the MCU does not provide a value for the RANDOM_CHK register, the I2C

transaction times out 10 ms after the RANDOM_GEN code is generated, and device is

ready for a new transaction.

Table 36. Secure bits

Bit

Description

ABIST OV1

AB_SW1_OV