MPF7100BVBA2ES datasheet(82/125 Pages) NXP

82 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

82 / 125

aaa-028069

10.4 µs

5.2 µs

5 %

fosc

10 %

fosc

time

SS_RANGE = 0

SS_RANGE = 1

fmod = 24 kHz

time

Figure 33. Spread-spectrum waveforms

If the frequency spread-spectrum is enabled, the switching regulators should be set in

PWM mode to ensure clock synchronization at all time.

If the external clock synchronization is enabled, (SYNCIN_EN = 1), the spread spectrum

is disabled regardless of the value of the FSS_EN bit.

15.7.5 Clock synchronization

An external clock can be fed via the SYNCIN pin to synchronize the switching regulators

to this external clock.

When the OTP_SYNCIN_EN = 0, the external clock synchronization is disabled. In this

case, the PLL is disabled, and the device always uses the internal high frequency clock

to generate the main frequency for the switching regulators.

When the OTP_SYNCIN_EN = 1, the external clock synchronization is enabled. In this

case, the internal PLL is always enabled and it uses either the internal high frequency

clock or the SYNCIN pin as it source to generate the main frequency for the switching

regulators.

If the SYNCIN function is not used, the pin should be grounded. If the external clock is

meant to start up after the PMIC has started, the SYNCIN pin must be maintained low

until the external clock is applied.

The SYNCIN pin is prepared to detect clock signals with a 1.8 V or 3.3 V amplitude and

within the frequency range set by the FSYNC_RANGE bit.

MPF7100BVBA2ES Datasheet(PDF) 82 Page - NXP Semiconductors