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MPF7100BVBA2ES Datasheet(PDF) 22 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 22 / 125 Table 15. VIN_OVLO specifications Symbol Parameter Min Typ Max Unit VIN_OVLO VIN overvoltage lockout rising [1] 5.6 5.8 6.0 V VIN_OVLO_HYS VIN overvoltage lockout hysteresis [1] — — 100 mV [1] Operating the device above the maximum VIN = 5.5 V for extended period of time may degrade and cause permanent damage to the device. 14.3 IC startup timing with PWRON pulled up The PF7100 features a fast internal core power up sequence to fulfill system power up timings of 5.0 ms or less, from power application until MCU is out of reset. Such requirement needs a maximum ramp up time of 1.5 ms for VIN to cross the UVDET threshold in the rising edge. A maximum core biasing time of 1.5 ms from VIN crossing to UVDET until the beginning of the power up sequence is ensured to allow up to 1.5 ms time frame for the voltage regulators power up sequence. Timing for the external regulators to start up is programmed by default in the OTP fuses. The 5.0 ms power up timing requirement is only applicable when the PWRON pin operates in level sensitive mode OTP_PWRON_MODE = 0, however turn on timing is expected to be the same for both level, or edge sensitive modes after the power on event is present. In applications using the VSNVSx regulator, if VSNVSx is required to reach regulation before system regulators come up, the system should use the SEQ[7:0] bits to delay the system regulators to allow enough time for VSNVSx to reach regulation before the power up sequence is started. |
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