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MPF7100BVBA2ES Datasheet(PDF) 68 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 68 Page - NXP Semiconductors |
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68 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 68 / 125 aaa-034301 I2C INTERFACE 2 to 3 MHz clock duty cycle generator slope compensation ISENSE DAC R2 R1 EA SW5FB TYPE II INTERNAL COMPENSATION VSW5 SW5LX SW5IN SW5 VIN CINSW5 COSW5 LSW5 SW5PHASE SW5ILIM SW5MODE CONTROLLER DRIVER Z2 + + Figure 29. Type 2 buck regulator block diagram Buck regulator SW5 uses 5 bits to set the output voltage. The VSW5[4:0] sets the output voltage during the run and the standby mode. The SW5 is designed to have a fixed voltage thought all the system operation. In the event a system requires this regulator to change its output voltage during the system- on states, when the SW5 is commanded to change its voltage via the I2C command, the output is discharged first and then enabled back to the new voltage level as stated in the VSW5[4:0] bits. The default output voltage configuration for the run and the standby modes is loaded from the OTP_VSW5[4:0] registers upon power up. Table 52. SW5 output voltage configuration Set point VSW5[4:0] VSW5FB (V) 0 0 0000 1.00 1 0 0001 1.10 2 0 0010 1.20 3 0 0011 1.25 4 0 0100 1.30 5 0 0101 1.35 6 0 0110 1.50 7 0 0111 1.60 8 0 1000 1.80 9 0 1001 1.85 10 0 1010 2.00 11 0 1011 2.10 12 0 1100 2.15 |
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