MPF7100BVBA2ES datasheet(43/125 Pages) NXP

43 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

43 / 125

The PWRON pin has two modes of operations as programed by the

OTP_PWRON_MODE bit.

When OTP_PWRON_MODE = 0, the PWRON pin operates in level sensitive mode. In

this mode, the device is in the corresponding OFF mode when the PWRON pin is pulled

low. Pulling the PWRON pin high is a necessary condition to generate a power on event.

PWRON may be pulled up to VSNVSx or VIN with an external 100 kΩ resistor, if device

is intended to come up automatically with VIN application. See Section 14.5 "Power up"

for details on power up requirements.

When OTP_PWRON_MODE = 1, the PWRON pin operates in edge sensitive mode. In

this mode, PWRON is used as an input from a push button connected to the PMIC.

When the switch is not pressed, the PWRON pin is pulled up to VIN externally through

a 100 kΩ resistor. When the switch is pressed, the PWRON pin should be shorted to

ground. The PWRON_S bit is high whenever the PWRON pin is at logic 0 and is low

whenever the PWRON pin is at logic 1.

The PWRON pin has a programmable debounce on the rising and falling edges as

shown in Table 29.

Table 29. PWRON debounce configuration in edge detection mode

Bits

Value

Falling edge debounce (ms)

Rising edge debounce (ms)

PWRON_DBNC[1:0]

125

PWRON_DBNC[1:0]

750

The default value for the power on debounce is set by the OTP_PWRON_DBNC[1:0]

bits.

Pressing the PWRON switch for longer than the debounce time starts a power on

event as well as generate interrupts which the processor may use to initiate PMIC state

transitions.

During the system-on states, when the PWRON button is pushed (logic 0) for longer than

the debounce setting, the PWRON_PUSH_I interrupt is generated. When the PWRON

button is released (logic 1) for longer than the debounce setting, the PWRON_REL_I

interrupt is generated.

The PWRON_1S_I, PWRON_2S_I, PWRON_3S_I, PWRON_4S_I and PWRON_8S_I

interrupts are generated when the PWRON pin is held low for longer than 1, 2, 3, 4 and 8

seconds respectively.

If PWRON_RST_EN = 1, pressing the PWRON for longer than the delay programmed by

TRESET[1:0] forces a PMIC reset. A PMIC reset initiates a power down sequence, wait

for 30 µs to allow all supplies to discharge and then it powers back up with the default

OTP configuration.

If PWRON_RST_EN = 0, the device starts a turn off event after push button is pressed

for longer than TRESET[1:0].

Table 30. TRESET configuration

TRESET[1:0]

Time to reset

2 s

4 s

8 s

MPF7100BVBA2ES Datasheet(PDF) 43 Page - NXP Semiconductors

MPF7100BVBA2ES Datasheet(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL