MPF7100BVBA2ES datasheet(31/125 Pages) NXP

Part #	MPF7100BVBA2ES

Description	7-channel power management integrated circuit for high performance applications

PDF	125 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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31 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

31 / 125

aaa-028056

120 µs

GRP3_DLY

120 µs

GRP2_DLY

120 µs

GRP1_DLY

10 µs

PWRON

PDWN_GRP1

GPR1_DLY = 120 µs

SW1

LDO1

RESETBMCU_DLY = 10 µS

PDWN_GRP2

GPR2_DLY = 120 µs

SW2

SW3

SW4

PDWN_GRP3

GPR3_DLY = 120 µs

LDO2

PDWN_GRP4

LDO2

SW2

SW3

SW4

RESETBMCU

SW1

LDO1

Figure 11. Group power down sequence example

14.6.2.3 Power down delay

After a power down sequence is started, the PWRON pin is masked until the sequence is

finished and the programmable power down delay is reached, the device can then power

up again if a power up event is present. The power down delay time can be programed

on OTP via the OTP_PD_SEQ_DLY[1:0] bits.

Table 23. Power down delay selection

OTP_PD_SEQ_DLY[1:0]

Delay after power down sequence

No delay

1.5 ms

5.0 ms

10 ms

MPF7100BVBA2ES Datasheet(PDF) 31 Page - NXP Semiconductors

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