MPF7100BVBA2ES datasheet(111/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

111 / 125

• Device test the UV comparators for each individual SWx and LDOx supply during the

self-test routine.

• During the ABIST verification, it is required to ensure the corresponding OV/UV

comparators are able to toggle, which in turn is a sign of the integrity of these functions.

• A warning bit is set on the I2C register map, if any of the comparators is not able to

toggle.

– The ABIST_OV1 register contains the AB_SWx_OV bits for all external regulators.

– The ABIST_OV2 register contains the AB_LDOx_OV bits for all external regulators.

– The ABIST_UV1 register contains the AB_SWx_UV bits for all external regulators.

– The ABIST_UV2 register contains the AB_LDOx_UV bits for all external regulators.

• The ABIST registers are cleared or overwritten each time the ABIST check is

performed.

• The ABIST registers are part of the secure registers and require an I2C secure write to

be cleared, if this feature is enabled.

Once ABIST check is performed, the PF7100 can proceed with the power up sequence

and the MCU should be able to request the value of these registers and learn if ABIST

failed for any of the voltage monitors.

The AB_RUN bit is provided to perform an ABIST verification on demand.

When the AB_RUN bit is set to 1, the control logic performs an ABIST verification on all

OV/UV monitoring circuits. When the ABIST verification is finished, the AB_RUN bit self-

clear to 0 and a new ABIST verification can be commanded as needed

When the Secure Write feature is enabled, the system must perform a secure write

sequence in order to start an ABIST verification on demand.

When the PF7100 performs an ABIST verification on demand, the OV/UV fault

monitoring is blanked for a maximum period of 200us. During this time, the system must

ensure it is in a safe state, or it is safe to perform this action without violating the safety

goals of the system.

If a failure on the OV/UV monitor is detected during the ABIST on-demand request, the

PMIC asserts the corresponding ABIST flags. The system is responsible to perform a

diagnostic check after each ABIST verification to ensure it places the system in Safe

state if an ABIST fault is detected.

19 IC level quiescent current requirements

Table 76. Quiescent current requirements

All parameters are specified at TA = −40 °C to 125 °C for AEC-Q100 grade 1 device, all parameters are specified at TA =

−40 °C to 105 °C for AEC-Q100 grade 2 device, unless otherwise noted. Typical values are characterized at VIN = 5.0 V and

TA = 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

ILPOFF

LP_Off state

LPM_OFF = 0

VIN > UVDET

VSNVSx = On

—

150

µA

IQPUOFF

QPU_Off

LPM_OFF = 1

System ready to power on

—

750

1000

µA

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