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MPF7100BVBA2ES Datasheet(PDF) 102 Page - NXP Semiconductors |
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MPF7100BVBA2ES Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 102 / 125 AD DR Register Name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 85 LDO1 CONFIG1 R/W LDO1_UV_ BYPASS LDO1_OV_BYPASS LDO1_ILIM_ BYPASS LDO1_UV_STATE LDO1_OV_STATE LDO1_ILIM_STATE LDO1_WDBYPASS LDO1_PG_EN 86 LDO1 CONFIG2 R/W LDO1_FLT_ REN LDO1_PDGRP[1:0] — — — LDO1_RUN_EN LDO1_STBY_EN 87 LDO1 PWRUP R/W LDO1_SEQ[7:0] 88 LDO1 RUN VOLT R/W — — — — VLDO1_RUN[3:0] 89 LDO1 STBY VOLT R/W — — — — VLDO1_STBY[3:0] 8B LDO2 CONFIG1 R/W LDO2_UV_ BYPASS LDO2_OV_BYPASS LDO2_ILIM_ BYPASS LDO2_UV_STATE LDO2_OV_STATE LDO2_ILIM_STATE LDO2_WDBYPASS LDO2_PG_EN 8C LDO2 CONFIG2 R/W LDO2_FLT_ REN LDO2_PDGRP[1:0] LDO2HW_EN VSELECT_EN — LDO2_RUN_EN LDO2_STBY_EN 8D LDO2 PWRUP R/W LDO2_SEQ[7:0] 8E LDO2 RUN VOLT R/W — — — — VLDO2_RUN[3:0] 8F LDO2 STBY VOLT R/W — — — — VLDO2_STBY[3:0] 9D VSNVS CONFIG1 R/W — — — — VSNVS2VOLT [1:0] VSNVS1VOLT [1:0] 9F PAGE SELECT R/TW — — — — — PAGE[2:0] 16.4 PF7100 QM OTP mirror register map (page 1) Reset types OFF_OTP Register loads the OTP mirror register values during power up OTP Register available in OTP bank only, reset from fuses when VIN crosses UVDET threshold VSNVS Reset when BOS has no valid input. VIN < UVDET AD DR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 A0 OTP FSOB SELECT — — — — OTP_FSOB_ SOFTFAULT OTP_FSOB_WDI OTP_FSOB_WDC OTP_FSOB_ HARDFAULT A1 OTP I2C — — — — OTP_I2C_CRC_EN OTP_I2C_ADD[2:0] A2 OTP CTRL1 — — OTP_EWARN_TIME[1:0] — OTP_STANDBYINV OTP_PG_ACTIVE OTP_PG_CHECK A3 OTP CTRL2 OTP_FSS_EN OTP_FSS_RANGE — OTP_XFAILB_EN OTP_VIN_OVLO_ SDWN OTP_VIN_OVLO_EN OTP_VIN_OVLO_DBNC[1:0] A4 OTP CTRL3 OTP_VTT_PDOWN OTP_SW3_VTTEN — — OTP_SW4CONFIG[1:0] OTP_SW1CONFIG[1:0] A5 OTP FREQ CTRL OTP_SW_MODE OTP_SYNCIN_EN OTP_SYNCOUT_EN OTP_FSYNC_ RANGE OTP_CLK_FREQ[3:0] A6 OTP SW RAMP OTP_SW4DVS_RAMP[1:0] OTP_SW3DVS_RAMP[1:0] OTP_SW2DVS_RAMP[1:0] OTP_SW1DVS_RAMP[1:0] A7 OTP PWRON — — OTP_PWRON_ MODE OTP_PWRON_DBNC[1:0] OTP_PWRON_ RST_EN OTP_TRESET[1:0] A8 OTP WD CONFIG — — OTP_WDI_MODE OTP_WDI_INV OTP_WD_EN OTP_WD_STBY_EN OTP_WDI_STBY_ ACTIVE OTP_WDWINDOW A9 OTP WD EXPIRE — — — — — OTP_WD_MAX_EXPIRE[2:0] AA OTP WD COUNTER OTP_WD_DURATION[3:0] OTP_WD_MAX_CNT [3:0] AB OTP FAULT COUNTERS — — — — OTP_FAULT_MAX_CNT[3:0] AC OTP FAULT TIMERS — — — — OTP_TIMER_FAULT[3:0] AD OTP PWRDN DLY1 OTP_GRP4_DLY[1:0] OTP_GRP3_DLY[1:0] OTP_GRP2_DLY[1:0] OTP_GRP1_DLY[1:0] AE OTP PWRDN DLY2 OTP_PD_SEQ_DLY[1:0] — — — — OTP_RESETBMCU_DLY[1:0] AF OTP PWRUP CTRL — OTP_PWRDWN_ MODE OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0] OTP_SEQ_TBASE[1:0] |
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