MPF7100BVBA2ES datasheet(124/125 Pages) NXP

124 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

124 / 125

Contents

Overview .............................................................. 1

Features ............................................................... 1

Simplified application diagram .......................... 1

Ordering information .......................................... 2

Applications .........................................................3

Internal block diagram ........................................4

Pinning information ............................................ 5

7.1

Pinning ...............................................................5

7.2

Pin definitions .................................................... 5

Absolute maximum ratings ................................6

ESD ratings ..........................................................7

Thermal characteristics ......................................7

Operating conditions ..........................................7

General description ............................................ 8

12.1

Features .............................................................8

12.2

Functional block diagram ...................................9

12.3

Power tree summary ......................................... 9

12.4

Device differences ........................................... 10

State machine ....................................................11

13.1

States description ............................................ 15

13.1.1

OTP/TRIM load ................................................15

13.1.2

LP_Off state .....................................................16

13.1.3

Self-test routine (ASIL B only) ......................... 16

13.1.4

QPU_Off state ................................................. 16

13.1.5

Power up sequence .........................................17

13.1.6

System-on states .............................................17

13.1.6.1 Run state ......................................................... 17

13.1.6.2 Standby state ...................................................18

13.1.7

WD_Reset ........................................................19

13.1.8

Power down state ............................................19

13.1.9

Fail-safe transition ........................................... 19

13.1.10 Fail-safe state (ASIL B only) ............................20

General device operation ................................. 21

14.1

UVDET .............................................................21

14.2

VIN OVLO condition ........................................ 21

14.3

IC startup timing with PWRON pulled up ......... 22

14.4

IC startup timing with PWRON pulled low

during VIN application ..................................... 23

14.5

Power up ......................................................... 25

14.5.1

Power up events ..............................................25

14.5.2

Power up sequencing ......................................25

14.6

Power down .....................................................28

14.6.1

Turn off events ................................................ 28

14.6.2

Power down sequencing ................................. 28

14.6.2.1 Sequential power down ................................... 29

14.6.2.2 Group power down .......................................... 29

14.6.2.3 Power down delay ........................................... 31

14.7

Fault detection ................................................. 32

14.7.1

Fault monitoring during power up state ............36

14.8

Interrupt management ..................................... 39

14.9

I/O interface pins ............................................. 41

14.9.1

PWRON ........................................................... 42

14.9.2

STANDBY ........................................................44

14.9.3

RESETBMCU .................................................. 44

14.9.4

INTB .................................................................44

14.9.5

XINTB .............................................................. 44

14.9.6

WDI ..................................................................45

14.9.7

EWARN ............................................................45

14.9.8

PGOOD ............................................................46

14.9.9

VSELECT .........................................................47

14.9.10 LDO2EN ...........................................................47

14.9.11 FSOB (safety output) .......................................48

14.9.11.1 FSOB active safe state (ASIL B device only) ... 48

14.9.11.2 FSOB fault safe state ...................................... 49

14.9.12 TBBEN .............................................................50

14.9.13 XFAILB .............................................................50

14.9.14 SDA and SCL (I2C bus) ..................................52

14.9.14.1 I2C CRC verification ........................................53

14.9.14.2 I2C secure write .............................................. 54

Functional blocks ..............................................55

15.1

Analog core and internal voltage references ....55

15.2

VSNVS LDOs .................................................. 56

15.3

Type 1 buck regulators (SW1 to SW4) ............ 58

15.3.1

SW3 VTT operation .........................................61

15.3.2

Multiphase operation ....................................... 62

15.3.3

Electrical characteristics .................................. 64

15.4

Type 2 buck regulator (SW5) .......................... 67

15.4.1

Electrical characteristics .................................. 71

15.5

Linear regulators ..............................................72

15.5.1

LDO load switch operation .............................. 74

15.5.2

LDO regulator electrical characteristics ........... 74

15.6

Voltage monitoring ...........................................75

15.6.1

Voltage monitoring architecture ....................... 77

15.6.2

Electrical characteristics .................................. 79

15.7

Clock management ..........................................79

15.7.1

Low frequency clock ........................................80

15.7.2

High frequency clock ....................................... 80

15.7.3

Manual frequency tuning ................................. 80

15.7.4

Spread-spectrum ............................................. 81

15.7.5

Clock synchronization ......................................82

15.8

Thermal monitors .............................................84

15.9

Analog multiplexer ........................................... 87

15.10

Watchdog event management .........................88

15.10.1 Internal watchdog timer ................................... 89

15.10.2 Watchdog reset behaviors ...............................91

I2C register map ................................................94

16.1

PF7100 ASIL B functional register map ...........95

16.2

PF7100 ASIL B OTP mirror register map

(page 1) ........................................................... 97

16.3

PF7100 QM functional register map .............. 100

16.4

PF7100 QM OTP mirror register map (page

1) ....................................................................102

OTP/TBB

and

hardwire

default

configurations ................................................. 104

17.1

TBB (Try Before Buy) operation .................... 104

17.2

OTP fuse programming ................................. 106

17.3

Default hardwire configuration ....................... 106

Functional safety .............................................110

18.1

System safety strategy .................................. 110

18.2

Output voltage monitoring with dedicated

band gap reference ....................................... 110

18.3

ABIST verification .......................................... 110

MPF7100BVBA2ES Datasheet(PDF) 124 Page - NXP Semiconductors

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