MPF7100BVMA2ES datasheet(16/125 Pages) NXP

16 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

16 / 125

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during

the system-on modes. By default, the LPM_OFF = 0 when VIN crosses the UVDET

threshold, therefore the state machine stops at the LP_Off state until a valid power up

event is present. When LPM_OFF= 1, the state machine transitions automatically to the

QPU_Off state if no power up event has been present and waits in the QPU_Off until a

valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current

(stay in LP_Off) or quick power up (move to QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error

is detected, the PF7100 ignores the power up event and remains in the LP_Off state to

avoid any potential damage to the system.

To be in LP_Off state, it is necessary to have VIN present.

13.1.3 Self-test routine (ASIL B only)

When device transitions from the LP_Off state, it turns on all necessary internal circuits

as it moves into the self-test routine and performs a self-check routine to verify the

integrity of the internal circuits.

During the self-test routine the following blocks are verified:

• The high-speed clock circuit is operating within a maximum of 15 % tolerance

• The output of both the voltage generation band gap and the monitoring band gap are

not more than 4 % to 12 % apart from each other

• A CRC is performed on the mirror registers during the self-test routine, to ensure the

integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal band gap and clocks, the self-test block

is executed up to 3 times (with 2.0 ms between each test), if a failure is encountered, the

state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the

corresponding ABIST flag for system information. The MCU is responsible for reading the

information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for more information about the functional safety strategy.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption off mode, in which all internal circuitry

required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state,

and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate

through I2C to access and modify the mirror registers in order to operate the device in

TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

hardwire default configurations".

MPF7100BVMA2ES Datasheet(PDF) 16 Page - NXP Semiconductors

MPF7100BVMA2ES Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL