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MPF7100BVMA2ES Datasheet(PDF) 23 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 23 / 125 aaa-028052 treg2reset tfirst Self Test RESETBMCU Regulator Outputs (enable signals) STEST done (internal signal) PWRON VSNVS1 V1P5D UVDET VIN Fuse Load 1.6 V tstest done Final VSNVS1 Regulation tvin_rise VSNVS2 Final VSNVS2 Regulation tvsnvs2_delay Figure 7. Startup with PWRON pulled up Table 16. Startup timing requirements (PWRON pulled up) Symbol Description Min Typ Max Unit tvin_rise Rise time of VIN from VPWR application to UVDET (system dependent) 10 — 1500 µs tstest_done Time from VIN crossing UVDET to STEST_ done going high (self-test performed and passed) — — 1.4 ms tvsnvs2_delay Time delay from fuse load to VSNVS2 start up — 2 — ms tfirst Time from STEST_done to first slot of power up sequence — — 100 µs treg2reset Time from first regulator enabled to RESETBMCU asserted to guarantee 5.0 ms PMIC boot up [1] — — 1.5 ms [1] External regulators power up sequence time (treg2reset) is programmed by OTP and may be longer than 1.5 ms. However, 1.5 ms is the maximum allowed time to ensure power up within 5.0 ms. 14.4 IC startup timing with PWRON pulled low during VIN application It is possible that PWRON is held low when VIN is applied. By default, LPM_OFF bit is reset to 0 upon crossing UVDET, therefore the PF7100 remains in the LP_Off state as described in Section 13.1.2 "LP_Off state". In this scenario, quiescent current in the LP_Off state is kept to a minimum. When PWRON goes high with LPM_OFF = 0, the PMIC startup is expected to take longer, since it has to enable most of the internal circuits and perform the self-test before starting a power up sequence. |
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