MPF7100BVMA2ES datasheet(83/125 Pages) NXP

83 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

83 / 125

• When the FSYNC_RANGE = 0, the input frequency range at SYNCIN pin should be

between 2000 kHz and 3000 kHz.

• When the FSYNC_RANGE = 1, the input frequency range at SYNCIN pin should be

between 333 kHz and 500 kHz.

The OTP_FSYNC_RANGE bit is used to select the default frequency range accepted in

the SYNCIN pin.

The external clock duty cycle at the SYNCIN pin should be between 40 % and 60 %. An

input frequency in the SYNCIN pin outside the range defined by the FSYNC_RANGE

bit is detected as invalid. If the external clock is not present or invalid, the device

automatically switches to the internal clock and sets the FSYNC_FLT_I interrupt, which in

turn asserts the INTB pin provided it is not masked.

The FSYNC_FLT_S bit is set to 1 as long as the input frequency is not preset or invalid,

and it is cleared to 0 when the SYNCIN has a valid input frequency.

The device switches back to the external switching frequency only when both, the

FSYNC_FLT_I interrupt has been cleared and the SYNCIN pin sees a valid frequency.

When the external clock is selected, the switching regulators should be set in PWM mode

to ensure clock synchronization at all time.

Upon an external clock failure, the MCU should verify the integrity of the external clock by

implementing a three-step diagnostic strategy.

1. MCU acknowledges and finds the source of the interrupt event.

2. The interrupt is generated by the FSYNC_FLT_I event, the MCU reads the

FSYNC_FLT_S bit to verify if the fault condition is persistent or not.

3. a. If FSYNC_FLT_S bit is 0, the fault condition can be considered as a transient

condition and the system is ready to switch over to the external clock by clearing

the FSYNC_FLT_I flag.

b. If the FSYNC_FLT_S bit is 1, the fault is considered a persistent fault and the MCU

must take corrective action to send the system to safe operation.

The system designer is responsible to define the tolerance time to allow the external

frequency to be lost before taking a corrective action such as stopping the system or

placing the system in safe state in safety-related applications.

The SYNCOUT pin is used to synchronize an external device to the PF7100.

The SYNCOUT pin outputs the main frequency used for the switching regulators in the

range of 2.0 MHz to 3.0 MHz. The SYNCOUT_EN bit can be used to enable or disable

the SYNCOUT feature via I2C during the system-on states.

• When SYNCOUT_EN = 0, the SYNCOUT feature is disabled and the pin is internally

pulled to ground.

• When SYNCOUT_EN = 1, the SYNCOUT pin toggles at the base frequency used by

the switching regulators.

The SYNCOUT function can be enabled or disabled by default by using the

OTP_SYNCOUT_EN bit.

MPF7100BVMA2ES Datasheet(PDF) 83 Page - NXP Semiconductors

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