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MPF7100BVMA2ES Datasheet(PDF) 98 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 98 Page - NXP Semiconductors |
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98 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 98 / 125 ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 A3 OTP CTRL2 OTP_FSS_EN OTP_FSS_RANGE — OTP_XFAILB_EN OTP_VIN_ OVLO_SDWN OTP_VIN_ OVLO_EN OTP_VIN_OVLO_DBNC[1:0] A4 OTP CTRL3 OTP_VTT_PDOWN OTP_SW3_VTTEN — — OTP_SW4ONFIG[1:0] OTP_SW1CONFIG[1:0] A5 OTP FREQ CTRL OTP_SW_MODE OTP_SYNCIN_ EN OTP_SYNCOUT_ EN OTP_FSYNC_ RANGE OTP_CLK_FREQ[3:0] A6 OTP SW RAMP OTP_SW4DVS_RAMP[1:0] OTP_SW3DVS_RAMP[1:0] OTP_SW2DVS_RAMP[1:0] OTP_SW1DVS_RAMP[1:0] A7 OTP PWRON — — OTP_PWRON_ MODE OTP_PWRON_DBNC[1:0] OTP_PWRON_RST_ EN OTP_TRESET[1:0] A8 OTP WD CONFIG — — OTP_WDI_ MODE OTP_WDI_INV OTP_WD_EN OTP_WD_ STBY_EN OTP_WDI_ STBY_ACTIVE OTP_ WDWINDOW A9 OTP WD EXPIRE — — — — — OTP_WD_MAX_EXPIRE[2:0] AA OTP WD COUNTER OTP_WD_DURATION[3:0] OTP_WD_MAX_CNT [3:0] AB OTP FAULT COUNTERS OTP_FS_MAX_CNT[3:0] OTP_FAULT_MAX_CNT[3:0] AC OTP FAULT TIMERS — OTP_FS_OK_TIMER[2:0] OTP_TIMER_FAULT[3:0] AD OTP PWRDN DLY1 OTP_GRP4_DLY[1:0] OTP_GRP3_DLY[1:0] OTP_GRP2_DLY[1:0] OTP_GRP1_DLY[1:0] AE OTP PWRDN DLY2 OTP_PD_SEQ_DLY[1:0] — — — — OTP_RESETBMCU_DLY[1:0] AF OTP PWRUP CTRL — OTP_PWRDWN_ MODE OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0] OTP_SEQ_TBASE[1:0] B0 OTP RESETBMCU PWRUP OTP_RESETBMCU_SEQ[7:0] B1 OTP PGOOD PWRUP OTP_PGOOD_SEQ[7:0] B2 OTP SW1 VOLT OTP_VSW1[7:0] B3 OTP SW1 PWRUP OTP_SW1_SEQ[7:0] B4 OTP SW1 CONFIG1 OTP_SW1UV_TH[1:0] OTP_SW1OV_TH[1:0] OTP_SW1_PDGRP[1:0] OTP_SW1ILIM[1:0] B5 OTP SW1 CONFIG2 OTP_SW1_LSELECT[1:0] OTP_SW1PHASE[2:0] — OTP_SW1_PG_ EN OTP_SW1_ WDBYPASS B6 OTP SW2 VOLT OTP_VSW2[7:0] B7 OTP SW2 PWRUP OTP_SW2_SEQ[7:0] B8 OTP SW2 CONFIG1 OTP_SW2UV_TH[1:0] OTP_SW2OV_TH[1:0] OTP_SW2_PDGRP[1:0] OTP_SW2ILIM[1:0] B9 OTP SW2 CONFIG2 OTP_SW2_LSELECT[1:0] OTP_SW2PHASE[2:0] — OTP_SW2_PG_ EN OTP_SW2_ WDBYPASS BA OTP SW3_ VOLT OTP_VSW3[7:0] BB OTP SW3 PWRUP OTP_SW3_SEQ[7:0] BC OTP SW3 CONFIG1 OTP_SW3UV_TH[1:0] OTP_SW3OV_TH[1:0] OTP_SW3_PDGRP[1:0] OTP_SW3ILIM[1:0] BD OTP SW3 CONFIG2 OTP_SW3_LSELECT[1:0] OTP_SW3PHASE[2:0] — OTP_SW3_PG_ EN OTP_SW3_ WDBYPASS BE OTP SW4 VOLT OTP_VSW4[7:0] BF OTP SW4 PWRUP OTP_SW4_SEQ[7:0] C0 OTP SW4 CONFIG1 OTP_SW4UV_TH[1:0] OTP_SW4OV_TH[1:0] OTP_SW4_PDGRP[1:0] OTP_SW4ILIM[1:0] C1 OTP SW4 CONFIG2 OTP_SW4_LSELECT[1:0] OTP_SW4PHASE[2:0] — OTP_SW4_PG_ EN OTP_SW4_ WDBYPASS CA OTP SW5 VOLT — — — OTP_VSW5[4:0] CB OTP SW5 PWRUP OTP_SW5_SEQ[7:0] CC OTP SW5 CONFIG1 OTP_SW5UV_TH[1:0] OTP_SW5OV_TH[1:0] OTP_SW5_PDGRP[1:0] OTP_SW5ILIM[1:0] CD OTP SW5 CONFIG2 OTP_SW5_LSELECT[1:0] OTP_SW5PHASE[2:0] — OTP_SW5_PG_ EN OTP_SW5_ WDBYPASS |
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