MPF7100BVMA2ES datasheet(79/125 Pages) NXP

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

79 / 125

15.6.2 Electrical characteristics

Table 66. VMON electrical characteristics

All parameters are specified at TA = −40 °C to 125 °C for AEC-Q100 grade 1 device, all parameters are specified at TA =

−40 °C to 105 °C for AEC-Q100 grade 2 device, unless otherwise noted. Typical values are characterized at VIN = 5.0 V,

VxFB = 1.5 V (Type 1 buck regulator), 3.3 V (Type 2 buck regulator, LDO regulator), and TA = 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

IQON

Block quiescent current, when block is enabled

One block per regulator

—

µA

IOFF

Block leakage current when disabled

—

500

tON_MON

Voltage monitor settling time after enabled

—

µs

VxFBUVHysteresis

Power good (UV) hysteresis

Voltage difference between UV rising and falling

thresholds

—

0.5

—

VUV_Tol

Undervoltage falling threshold accuracy

With respect to target feedback voltage tolerance

For type 2 switching regulator and LDO regulator

For type 1 switching regulator when VSWxFB > 0.75 V

−2

—

VUV_Tol

Under voltage falling threshold accuracy

With respect to target feedback voltage

For type 1 switching regulator when VSWxFB ≤ 0.75 V

−3

—

Power good (UV) debounce time UV_DB = 00

2.5

5.0

7.5

Power good (UV) debounce time UV_DB= 01

Power good (UV) debounce time UV_DB= 10

tUV_DB

Power good (UV) debounce time UV_DB = 11

µs

VOV_Tol

Overvoltage rising threshold accuracy

With respect to target feedback voltage tolerance

For type 2 switching regulator and LDO regulators

For type 1 switching regulator when VSWxFB > 0.75 V

−2

—

VOV_Tol

Overvoltage rising threshold

With respect to target feedback voltage tolerance

For type 1 switching regulator when VSWxFB ≤ 0.75 V

−3

—

VxFBOVHysteresis

Overvoltage (OV) hysteresis

Voltage difference between OV rising and falling

thresholds

0.5

—

1.0

Overvoltage (OV) debounce time OV_DB = 00

Overvoltage (OV) debounce time OV_DB = 01

Overvoltage (OV) debounce time OV_DB = 10

105

tOV_DB

Overvoltage (OV) debounce time OV_DB = 11

125

160

µs

15.7 Clock management

The clock management provides a top-level management control scheme of internal

clock and external synchronization intended to be primarily used for the switching

regulators. The clock management incorporates various subblocks:

• Low power 100 kHz clock

• Internal high frequency clock with programmable frequency

• Phase-Locked Loop (PLL)

A digital clock management interface is in charge of supporting interaction among these

blocks.

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