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MPF7100BVMA2ES Datasheet(PDF) 35 Page - NXP Semiconductors |
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MPF7100BVMA2ES Datasheet(HTML) 35 Page - NXP Semiconductors |
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35 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 35 / 125 When a regulator experiences a fault event, a fault timer is started. While this timer is in progress, the expectation is that the processor takes actions to clear the fault. For example, it could reduce its load in the event of a current limit fault, or turn off the regulator in the event of an overvoltage fault. If the fault clears before the timer expires, the state machine resumes the normal operation, and the fault timer gets reset. If the fault does not clear before the timer expires, a power down sequence is initiated to turn off the voltage regulators. The default value of the fault timer is set by the OTP_TIMER_FAULT[3:0], however the duration of the fault timer can be changed during the system-on states by modifying the TIMER_FAULT[3:0] bits in the I2C registers. Table 25. Fault timer register configuration OTP bits OTP_TIMER_FAULT [3:0] Functional bits TIMER_FAULT [3:0] Timer value (ms) 0000 0000 1 0001 0001 2 0010 0010 4 0011 0011 8 0100 0100 16 0101 0101 32 0110 0110 64 0111 0111 128 1000 1000 256 1001 1001 512 1010 1010 1024 1011 1011 2056 1100 1100 Reserved 1101 1101 Reserved 1110 1110 Reserved 1111 1111 Disabled Each voltage regulator has a dedicated I2C bit that is used to bypass the fault detection mechanism for each specific fault. SWx_ILIM_BYPASS / LDOx_ILIM_BYPASS • 0 = ILIM protection enabled • 1 = ILIM fault bypassed SWx_OV_BYPASS / LDOx_OV_BYPASS • 0 = OV protection enabled • 1 = OV fault bypassed SWx_UV_BYPASS / LDOx_UV_BYPASS • 0 = UV protection enabled • 1 = UV fault bypassed |
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